Refinement of semiconductor devices such as an LSI is increasingly advanced, and some semiconductor products on the market have a wiring width of the order of submicron.
On the other hand, circuit boards on which semiconductor devices are mounted have a minimum wiring width of ten and several microns, which is greater by two orders of magnitude than the wiring width of semiconductor devices. In order to increase the speed of electronic devices and further miniaturize portable devices, semiconductor devices needs to be mounted on circuit boards with higher density, and for this purpose as well, reduction of the wiring width of the circuit boards is desired.
As a wiring formation method for circuit boards, the subtraction method, the semi-additive method, the imprint method, and others are known.
Among them, the subtraction method is that in which a wiring is formed by wet-etching a conductive film, using a resist pattern as a mask. Since the etching progresses isotropically, this method is disadvantageous in forming fine wiring, and is capable of only achieving a minimum wiring width of the order of 35 μm.
In the semi-additive method, after a seed layer is formed on an insulating layer, a plating resist is formed thereon, and then, a conductive film is formed in openings of the plating resist by electrolysis plating while power is supplied to the seed layer. After the plating resist is removed, the seed layer is wet-etched, thereby forming a wiring formed of the remaining conductive film which has not been etched.
Such semi-additive method allows the wiring width to be reduced as compared with the subtraction method. However, when the wiring width is of the order of 5 μm or less, it is difficult to form a wiring in a stable shape, and adhesion between the wiring and the underlying substrate is reduced. For these reasons, the semi-additive method is used to form a wiring of a width greater than 10 μm in many cases.
On the other hand, in the imprint method, a wiring groove or a hole is formed in a resin layer by engraving the resin layer with projections and depressions on the surface of a conductor plate (stamper). After the wiring groove is formed, a conductive film is formed in the wiring groove by an electroplating method or the like, and an excessive conductive film on the resin layer is removed by CMP (Chemical Mechanical Polishing) or the like to form a wiring in the wiring groove.
However, when the imprint method is used for forming a wiring in fine and complex shape, there occurs a problem that when the conductor plate is released from the resin layer, a part of the resin layer adheres to the conductor plate to damage the wiring groove. In addition, the imprint method has another problem in that the projections and depressions in the wiring shape formed on the conductor plate are deformed over repeated use of the conductor plate.
Note that the related techniques are disclosed in Japanese Laid-open Patent Publications No. 2007-36217, No. 2006-100463, No. 2005-5721, No. 2006-303438, and No. 2008-84958.